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TLE7181EM h-bridge and dual half bridge driver ic data sheet, rev 1.1, sept. 2010 automotive power
data sheet 2 rev 1.1, 2010-09-30 h-bridge and dual ha lf bridge driver ic TLE7181EM table of contents 1 overview 3 2 block diagram 4 3 pin configuration 5 3.1 pin assignment 5 3.2 pin definitions and functions 5 4 general product characteristics 7 4.1 absolute maximum ratings 7 4.2 functional range 8 4.3 thermal resistance 9 4.4 default state of inputs 9 5 description and electrical characteristics 10 5.1 mosfet driver 10 5.1.1 driving mosfet output stages 10 5.1.2 mosfet outp ut stages 10 5.1.3 dead time 11 5.1.4 bootstrap principle 11 5.1.5 100% d.c. charge pumps 12 5.1.6 reverse polarity prot ection of motor bridge 12 5.1.7 sleep mode 12 5.1.8 wake up 12 5.1.9 electrical characteristics 13 5.2 protection and diagnostic functions 17 5.2.1 state diagram of different operation modes 17 5.2.2 short circuit protection 18 5.2.3 scdl pin open detection 18 5.2.4 vs and vdh over voltage warning 18 5.2.5 vs under voltage shutdown 18 5.2.6 vreg under voltage warning 18 5.2.7 over temperature warning 19 5.2.8 over current warning 19 5.2.9 passive gxx clamping 19 5.2.10 e rr pin 19 5.2.11 electrical characteristics 21 5.3 shunt signal conditioning 23 5.3.1 electrical characteristics 23 6 application information 25 6.1 layout guide lines 26 6.2 further application information 26 7 package outlines 27 8 revision history 28 table of contents
pg-ssop-24 type package marking TLE7181EM pg-ssop-24 TLE7181EM data sheet 3 rev 1.1, 2010-09-30 h-bridge and dual half bridge driver ic TLE7181EM 1overview features ? pwm/dir-interface drives 4 n-channel power mosfets ? unlimited d.c. switch on ti me of low and highside mosfets ? 0 ?95% at 20khz & 100% duty cycle of high side mosfets ? 0 ... 100 % duty cycle of low side mosfets ? additional output to drive a reverse polarity protection n-mosfet ? current sense opamp ? low quiescent current mode ? internal shoot through protection ? adjustable dead time ? 1 bit diagnosis / err ? over current warning based on current sense opamp with fixed warning level ? analog adjustable short circuit protection levels via scdl pin with open pin detection ? over temperature warning ? over voltage warning ? under voltage warning and shutdown ? green product (rohs compliant) ? aec qualified description the TLE7181EM is a h-bridge driver ic dedicated to control 4 n-channel mosfets typically forming the converter for a high current dc motor drives in the automotive sect or. it incorporates several protection features such as over current and short circuit dete ction as well as under-, over volt age and over temperature diagnosis. typical applications are fans, pumps and electric powe r steering. the TLE7181EM is designed for a 12v power net. table 1 product summary specified operating voltage v sop 7.0 v ? 34 v junction temperature t j -40 c .. 150c maximum output source resistance r sou 13.5 maximum output sink resistance r sink 9 maximum quiescent current 1) 1) typical value at t j =25c c i qvs 8 a
h-bridge and dual ha lf bridge driver ic TLE7181EM block diagram data sheet 4 rev 1.1, 2010-09-30 2 block diagram figure 1 block diagram TLE7181EM ena bh1 sh1 gh1 gl1 sh2 gh2 gl2 vreg vreg floating hs driver short circuit detection floating ls driver short circuit detection floating hs driver short circuit detection floating ls driver short circuit detection l e v e l s h i f t e r diagnostic logic under voltage over voltage over current overtemperature short circuit reset ____ err iso scdl gnd bh2 vs vdh sl isp isn charge pump hs1 charge pump hs2 rpp rpp pwm dir input control dead time dt drv dis shunt signal conditioning over current detection
data sheet 5 rev 1.1, 2010-09-30 h-bridge and dual ha lf bridge driver ic TLE7181EM pin configuration 3 pin configuration 3.1 pin assignment figure 2 pin configuration 3.2 pin definitions and functions # of pins symbol function 1 bh2 pin for + terminal of the bo otstrap capacitor of phase 2 2 gh2 output pin for gate of high side mosfet 2 3 sh2 pin for source connecti on of high side mosfet 2 4 gl2 output pin for gate of low side mosfet 2 5 vdh voltage input common drain high side for short circuit detection 6 rpp charge pump output for reverse polarity protection of the motor bridge 7 vs pin for supply voltage 8 vreg output of supply for driver output stage - connect to a capacitor 9 ena input pin for reset of err registers, active switch off of external mosfets and low quiescent current mode, set high to enable operation 10 isn input for opamp + terminal 11 isp input for opamp - terminal 12 iso output of opamp 13 dt input for adjustable dead time fu nction, connect to gnd via resistor 14 drvdis disable dir/pwm interface & all output stages switched off 15 pwm control input for pwm frequency and duty cycle 16 dir control input for spinni ng direction of the motor bh1 gh1 sh1 gl1 sl gnd scdl vs vreg ena isn isp iso bh2 gh2 sh2 gl2 vdh rpp ___ err dir pwm drvdis dt 18 17 16 15 14 13 24 23 22 21 20 19 1 2 3 4 5 6 7 8 9 10 11 12
h-bridge and dual ha lf bridge driver ic TLE7181EM pin configuration data sheet 6 rev 1.1, 2010-09-30 17 err push pull output stage 18 scdl input pin for adjustable short circuit detection function 19 gnd ground pin 20 sl pin for common source of lowside mosfets 21 gl1 output pin for gate of low side mosfet 1 22 sh1 pin for source connection of high side mosfet 1 23 gh1 output pin for gate of high side mosfet 1 24 bh1 pin for + terminal of the bootstrap capacitor of phase 1 tab tab should be connected to gnd # of pins symbol function
data sheet 7 rev 1.1, 2010-09-30 h-bridge and dual ha lf bridge driver ic TLE7181EM general product characteristics 4 general product characteristics 4.1 absolute maximum ratings absolute maximum ratings 1) 40 c t j 150 c ; all voltages with respect to ground, positive cu rrent flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. max. voltages 4.1.1 supply voltage at vs v vs -0.3 45 v ? 4.1.2 supply voltage at vs v vsrp -4.0 45 v r vs 10 4.1.3 voltage range at vdh v vdh -0.3 55 v ? 4.1.4 voltage range at rpp v rpp -0.3 55 v ? 4.1.5 maximum current at rpp i rpp -25 25 ma ? 4.1.6 voltage range at ena v ena -0.3 45 v ? 4.1.7 voltage range at scdl v scdl -0.3 6 v ? 4.1.8 voltage range at pwm, dir, dt, drvdis v dpi -0.3 6 v ? 4.1.9 voltage range at err , iso v dpo -0.3 6 v ? 4.1.10 voltage range at isp, isn v opi -5.0 5.0 v ? 4.1.11 voltage range at vreg v vreg -0.3 15 v ? 4.1.12 voltage range at bhx v bh -0.3 55 v ? 4.1.13 voltage range at ghx v gh -0.3 55 v ? 4.1.14 voltage range at ghx v ghp -7.0 55 v t p <1s; f =50khz 4.1.15 voltage range at shx v sh -2.0 45 v ? 4.1.16 voltage range at shx v shp -7.0 45 v t p <1s; f =50khz 4.1.17 voltage range at glx v gl -0.3 18 v ? 4.1.18 voltage range at glx v glp -7.0 18 v t p <0.5s; f =50khz 4.1.19 voltage range at sl v sl -1.0 5.0 v ? 4.1.20 voltage range at sl v slp -7.0 5.0 v t p <0.5s; f =50khz; c bs 330nf 4.1.21 voltage difference gxx-sxx v gs -0.3 15 v ? 4.1.22 voltage difference bhx-shx v bs -0.3 15 v ? temperatures 4.1.23 junction temperature t j -40 150 c? 4.1.24 storage temperature t stg -55 150 c? 4.1.25 lead soldering temperature (1/16?? from body) t sol ?260 c? 4.1.26 peak reflow soldering temperature 2) t ref ?260 c? power dissipation 4.1.27 power dissipation (dc) p tot ?2w?
h-bridge and dual ha lf bridge driver ic TLE7181EM general product characteristics data sheet 8 rev 1.1, 2010-09-30 note: stresses above the ones listed here may cause perm anent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: integrated protection functions are designed to prevent ic destruction under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. protection functions are not designed for continuous repetitive operation. 4.2 functional range esd susceptibility 4.1.28 esd resistivity 3) v esd ?2kv 4.1.29 cdm v cdm ?1kv 1) not subject to production test, specified by design. 2) reflow profile ipc/jedec j-std-020c 3) esd susceptibility hbm according to eia/jesd 22-a 114b pos. parameter symbol limit values unit conditions min. max. 4.2.1 specified supply voltage range v vs1 7.0 34 v ? 4.2.2 supply voltage range 1) 1) operation above 34v limited by max. allowed power dissipation and max. ratings v vs2 5.5 45 v v vs <7v reduced functionality 4.2.3 quiescent current at vs i qvs1 ?8 a v vs , v vdh =12v; ena=low; t j =25c 4.2.4 quiescent current at vs i qvs2 ?10a v vs , v vdh <15v; ena=low; t j 85c 4.2.5 quiescent current at vdh i qvdh1 ?8 a v vs , v vdh =12v; ena=low; t j =25c 4.2.6 quiescent current at vdh i qvdh2 ?10a v vs , v vdh <15v; ena=low; t j 85c 4.2.7 supply current at vs (device enabled) 2) 2) current can be higher, if driv er output stages are unsupplied i vs(1) ? 22 ma no switching 4.2.8 supply current at vs (device enabled) i vs(2) ?45ma4x q gs x f pwm 20ma ; v vs =7.0..34v 4.2.9 d.c. switch on time of output stages d dc ? s? 4.2.10 duty cycle highside output stage 3) 3) max. limit of d.c. will increase, if f pwm or external gate charge of the mosfets is reduced d hs 095% f pwm =20khz; continuous operation; c bs 330nf 4.2.11 duty cycle lowside output stage d ls 0100%? absolute maximum ratings (cont?d) 1) 40 c t j 150 c ; all voltages with respect to ground, positive cu rrent flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. max.
data sheet 9 rev 1.1, 2010-09-30 h-bridge and dual ha lf bridge driver ic TLE7181EM general product characteristics the pwm frequency is limited by thermal constraints and the maximum duty cycle (minimum charging time of bootstrap capacitor). note: within the functional range the ic operates as de scribed in the circuit description. the electrical characteristics are specifi ed within the conditions given in the re lated electrical ch aracteristics table. 4.3 thermal resistance note: this thermal data was generated in accordance wit h jedec jesd51 standards. fo r more information, go to www.jedec.org . 4.4 default state of inputs table 2 default state of inputs (if left open) pos. parameter symbol limit values unit conditions min. typ. max. 4.3.1 junction to case 1) 1) not subject to production test, specified by design. r thjc ??5k/w? 4.3.2 junction to ambient 1) r thja ?35?k/w 2) 2) exposed heatslug package use this sentence : specified r thja value is according to jedec jesd51-2,-5,-7 at natural convection on fr4 2s2p board; the product (chip+package) wa s simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70m cu, 2 x 35m cu). where applicable a thermal via array under the ex posed pad contacted the first inner copper layer. characteristic state remark default state of pwm and dir low low side mosfets off and highside mosfets on default state of dt open maximum deadtime default state of ena low output stages disabled device in sleep mode default state of scdl open short circuit detection deactivation & warning default state of drvdis high all out put stages off & no error will be reported
h-bridge and dual ha lf bridge driver ic TLE7181EM description and electrical characteristics data sheet 10 rev 1.1, 2010-09-30 5 description and electr ical characteristics 5.1 mosfet driver 5.1.1 driving mosfet output stages the TLE7181EM incorporates 2 high side and low side output stages for 4 external mosfets. the 4 mosfet output stages will be dr iven by the pwm/dir interface. with the pwm/dir interf ace only 2 inputs pins are necessary to drive a typical h-bridge topology fo r a dc-brush motor. the rotation direction of the motor can be chosen with the input pin dir. the speed of the motor can is controlled by applying a pwm-signal at pin pwm. the drvdis pin allows to switch off all 4 mosfets. table 3 provides an overview of the different states with this interface. table 3 pwm/dir interface normal operation 5.1.2 mosfet output stages the six push-pull mosfet driver stages of the TLE7181EM are realized as separate floating blocks. this means that the output stage is follows the individual mosfet source voltages and so ensuring stable mosfet driving even in harsh electrical environment. all 4 output stages have the same output power and thanks to the used bootstrap prin ciple they can be switched all up to high frequencies. each output stage has its own short circuit detection bl ock. for more details about short circuit detection see chapter 5.2.2 . drvdis dir pwm highside switch1 lowside sw itch1 highside switch2 lowside switch2 000on off on off 001on off off on 010on off on off 0 1 1 off on on off 1 x x off off off off
data sheet 11 rev 1.1, 2010-09-30 h-bridge and dual ha lf bridge driver ic TLE7181EM description and electrical characteristics figure 3 block diagram of driver stages including short circuit detection 5.1.3 dead time in bridge applications it has to be assured that the exte rnal high side and low side mosfets are not ?on? at the same time, connecting directly the battery voltage to gnd. the dead time generated in the TLE7181EM can be programmed by applying an resistor betw een the dt pin and gnd. higher extern al resistor values lead to higher dead time. a minimum dead time applied, if the dt pin is connected to gnd. the typical dead time can be calc ulated with the following formula: if an exact dead time of the bridge is needed, t he use of the c pwm generation unit is recommended. 5.1.4 bootstrap principle the TLE7181EM provides a bootstrap based supply for its high side output stages. the bootstrap capacitors are charged by switching on the external low side mosfets, connecting the bootstrap capacitor to gnd. under this condit ion the bootstrap capacitor will be char ged from the vreg capacitor via the integrated bootstrap diode. if the low side mosfet is s witched off and the high side mosfet is switched on, the bootstrap capacitor will float together wit h the shx voltage to the supply voltag e of the bridge. un der this condition the supply current of the high side ou tput stage will discharge the bootstrap capacitor. this curr ent is specified. the size of the capacitor together wi th this current w ill determine how long the high side mosfet can be kept on without recharging the bootstrap capacitor. ghx shx vdh v sc p + - level shifter floating hs dr iver 2 x glx sl v sc p + - level shifter floating ls driver 2 x vreg voltage regulator bhx vreg ena vs error logic reset power on reset ____ err shor t circuit filter scd scd scd input logic dead time lock / unlock pwm dir on / off on / off gnd dt shor t circuit detection level scdl vdh vreg blanking drvdis char ge pum p rpp ] [ 4 4 . 2 02 . 0 081 . 0 ] [ + + = k rdt deadtime s t
h-bridge and dual ha lf bridge driver ic TLE7181EM description and electrical characteristics data sheet 12 rev 1.1, 2010-09-30 5.1.5 100% d.c. charge pumps 100% d.c. charge pumps are implemented for each high side output stage. therefore th e high side output stages can be switch on for an unlimited ti me. these integrated charge pumps can handle le akage currents which will be caused by external mosfets and the TLE7181EM itself. they are not strong enough to drive a 99% duty cycle for a longer time. the charge pumps are running when the dr iver is not in sleep mode and assure that the bootstrap capacitors are charged as long as the user does not apply critical duty cycle for a longer time. 5.1.6 reverse polarity pr otection of motor bridge the TLE7181EM provides an additional rpp pin to protect motor bridge for reverse polarity. this rpp pin can drive an additional external n-channel power mosfet designed in between battery and the motor bridge. the rpp pin is internally supplied by the two integrated 100% d.c. charge pumps. they are especially designed to handle additional current which is needed to drive a the gate charge of the reverse polarity mosfet. the guarantied output current of the charge pumps is specified. 5.1.7 sleep mode if ena pin is set to low, the err flag will be set to low and the outp ut stages will be switched off. after ena pin is kept low for t lqm the sleep mode of the driver ic will be activated. in sleep mode the complete chip is deactivated. this means the inte rnal supply structur e of the TLE7181EM will be switched off. this mode is design ed for lowest current consumption from the power net of the car. the passive clamping is active. for details see the description of passive clamping, see chapter 5.2.9 . the TLE7181EM will wake up, if ena is set to high.the ena pin is 45v compatible, so ena can be directly be connected to the ignition key signal kl15. 5.1.8 wake up a special start up procedure is implemented into the TLE7181EM to guarantee charged bootstrap capacitors. this start up procedure is automatically performe d before normal h-bridge mo tor control with pwm/dir is possible. if the ena pin is set to high, the vreg voltage starts to increase. as soon as the under voltage threshold vreg_uv is reached, both low side output stages will be sw itched on for a short period of time for fast charging of the bootstrap capacitors. when the bootstrap capacitor voltage is high enough the auto start up procedure is completed and the low side mosfets will be driven accoring the input pattern. during wake up procedure the err signal is set to low. it will be set to high , if no error occurs at the TLE7181EM and auto start procedure is completed. to assure that the driver is finally in the normal operat ion mode, it is recommended to set the drvdis pin to high for minimum 1us. after that procedure the out put stages can be driven by pwm/dir interface.
data sheet 13 rev 1.1, 2010-09-30 h-bridge and dual ha lf bridge driver ic TLE7181EM description and electrical characteristics 5.1.9 electrical characteristics electrical characteristics mosfet drivers v s = 7.0 to 34v, t j = -40 to +150 c all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. control inputs 5.1.1 low level inpu t voltage of pwm; dir v i_ll ??1.0v? 5.1.2 high level input voltage of pwm; dir v i_hl 2.0??v? 5.1.3 input hysteres is of pwm; dir d vi 100 200 ? mv ? 5.1.4 pwm; dir pull-down resistors to gnd r il 20 ? 50 k ? 5.1.5 low level input voltage of ena v e_ll ? ? 0.75 v ? 5.1.6 high level input voltage of ena v e_hl 2.1??v? 5.1.7 input hysteresis of ena d ve 50 200 ? mv ? 5.1.8 ena pull-down resistor to gnd r il 70 125 200 k ? 5.1.9 low level input voltage of drvdis v d_ll ??1.0v? 5.1.10 high level input voltage of drvdis v d_hl 2.0??v? 5.1.11 input hysteresis of drvdis d vd 100 200 ? mv ? 5.1.12 drvdis pull-up resistor to internal supply r dh 30 50 80 k ? mosfet driver output 5.1.13 output so urce resistance r sou 2?13.5 i load =-20ma 5.1.14 output sink resistance r sink 2?9.0 i load =20ma 5.1.15 high level output voltage gxx vs. sxx v gxx1 ?1115v13.5v v vs 34v; i load =0ma 5.1.16 high level output voltage gxx vs. sxx v gxx2 ?1113.5v13.5v v vs 34v; c load =20nf; d.c.=50%; f pwm =20khz 5.1.17 high level output voltage ghx vs. shx 1) v ghx3 ? v vs -1.5 ? v 7.0v h-bridge and dual ha lf bridge driver ic TLE7181EM description and electrical characteristics data sheet 14 rev 1.1, 2010-09-30 5.1.19 high level output voltage ghx vs. shx 1)2) v ghx4 5.0 + v diode ??v v vs =7.0v; c load =20nf; d.c.=95%; f pwm =20khz; passive freewheeling 5.1.20 high level output voltage ghx vs. shx 1) v ghx5 5.0??v v vs =7.0v; c load =20nf; d.c.=95%; f pwm =20khz 5.1.21 high level output voltage glx vs. slx 1) v glx5 6.0??v v vs =7.0v; c load =20nf; d.c.=95%; f pwm =20khz 5.1.22 high level output voltage ghx vs. shx 1) v ghx5 10 ? ? v 7.0v v vs 13.5v; c load =20nf; d.c.=100% 5.1.23 high level output voltage glx vs. slx 1) v glx5 6.5??v v vs =7.0v; c load =20nf; d.c.=100% 5.1.24 rise time t rise ?250?ns c load =11nf; r load =1 ; v vs =7v; 20-80% 5.1.25 fall time t fall ? 200 ? ns 5.1.26 high level output voltage (in passive clamping) 1) v gxxuv ? ? 1.2 v sleep mode or vs_uvlo 5.1.27 pull-down resistor at bhx to gnd r bhuvx ??85k sleep mode or vs_uvlo 5.1.28 pull-down resistor at vreg to gnd r vruv ??30k sleep mode or vs_uvlo 5.1.29 bias current into bhx i bhx ??150a v cbs >5v; no switching 5.1.30 bias current out of shx i shx ?40?a v shx = v sl ; ena=high; affected highside output stage static on; v cbs >5v 5.1.31 bias current out of sl i sl ??1.4ma 0 v shx v vs +1v; ena=high; no switching; v cbs >5v electrical characteristics mosfet drivers v s = 7.0 to 34v, t j = -40 to +150 c all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max.
data sheet 15 rev 1.1, 2010-09-30 h-bridge and dual ha lf bridge driver ic TLE7181EM description and electrical characteristics dead time & input propagation delay times 5.1.32 programmable internal dead time t dt 0.08 0.25 0.82 1.0 2.0 0.13 0.42 1,21 1.88 3.62 0.20 0.57 1.65 2.7 5.6 s r dt =0k r dt =10k r dt =47k r dt =100k r dt =1000k 5.1.33 max. internal dead time t dt_max 2.3 4.0 6.4 s dt pin open 5.1.34 dead time deviation between channels d tdt1 -20 ? 20 % ? -15 ? 15 % r dt 47k 5.1.35 dead time deviation between channels lsoff -> hs on d tdth1 -14 ? 14 % ? -12 ? 12 % r dt 47k 5.1.36 dead time deviation between channels hsoff -> ls on d tdtl1 -14 ? 14 % ? -12 ? 12 % r dt 47k 5.1.37 input propagation time (low on) t p(iln) 0 100 200 ns c load =10nf; r load =1 5.1.38 input propagation time (low off) t p(ilf) 0 100 200 ns 5.1.39 input propagation time (high on) t p(ihn) 0 100 200 ns 5.1.40 input propagation time (high off) t p(ihf) 0 100 200 ns 5.1.41 absolute input propagation time difference between above propagation times t p(diff) ? 50 100 ns vreg 5.1.42 vreg output voltage v vreg 11 12.5 14 v v vs 13.5v; i load =-35ma 5.1.43 vreg over current limitation i vregocl 100 ? 500 ma ? 3) 5.1.44 voltage drop between vs and vreg v vsvreg ??0.5v v vs 7v; i load =-35ma; ron operation 100% d.c. charge pump 5.1.45 charge pump frequency 1) f cp ?21?mhz? motor bridge reverse polarity protection output 5.1.46 high level output voltage rpp vs. vs v rpp1 ?1115v i load =0a 5.1.47 high level output voltage rpp vs. vs v rpp2 ?1112.5v i load -30a 5.1.48 d.c. output current at rpp i rpp1 ?-110-150a v rpp 10v; lowside on 5.1.49 rise time 1) t rpprise ?12ms c load =10nf 5.1.50 rise time 1) t rpprise ?1020s c load =100pf electrical characteristics mosfet drivers v s = 7.0 to 34v, t j = -40 to +150 c all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max.
h-bridge and dual ha lf bridge driver ic TLE7181EM description and electrical characteristics data sheet 16 rev 1.1, 2010-09-30 ena and low quiescent current mode 5.1.51 ena propagation time to output stages switched off t pena_h-l ?2.03.0s? 5.1.52 low time of ena signal without clearing error register t rst0 ??1.2s? 5.1.53 high time of ena signal after ena rising edge for error logic active t rst1 45.757s? 5.1.54 go to sleep time t sleep 310 415 540 s ? 5.1.55 wake up time t wake ?50100s c reg =2.2f; c bs =330nf 1) not subject to production test, specified by design. 2) v diode is the bulk diode of the external low side mosfet 3) normally no error flag; error flag might by triggered by under voltage vreg caused by very high load current electrical characteristics mosfet drivers v s = 7.0 to 34v, t j = -40 to +150 c all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max.
data sheet 17 rev 1.1, 2010-09-30 h-bridge and dual ha lf bridge driver ic TLE7181EM 5.2 protection and diagnostic functions 5.2.1 state diagram of different operation modes figure 4 state diagramTLE7181EM sleep mode - low quiescent current - all supplies switched off wake-up mode - error is reported - auto start mode with lowside switched-on phases latched error mode : scd - latched error is reported - mosfets switched -off - vreg and vdd on normal mode without error conditions - no error is reported - driver stages are active warning mode: ocd/ovd/otd - error is reported - driver stages are active ena = high wake-up time expired short circuit detection ena=low ena = high ?&? go to sleep time not expired error conditions tle 7181em and used abbreviations : warnings: over current detection ( ocd ) vs/vdh over voltage detection ( ovd ) scdl pin open detection ( scdlpod ) over temperature detection ( otd ) errors: vreg under voltage error ( vreg_uv ) vs under voltage lockout ( vs_uvlo ) short circuit detection ( scd ) * vs_uvlo: leads from every mode into the sleep mode ** ena = low: leads from every mode into the go to sleep mode go-to-sleep mode - mosfets switched -off - error is reported non latched error mode: vreg_uv/scdlpod - error is reported - mosfets switched -off vs_uvlo error mode - error is reported - mosfets switched-off - vreg and charge pump off *) vs_uvlo ena = low ?&? go to sleep time expired no scd ?&? ena reset warning detection no warning vreg_uv/scdl pin open no vreg_uv/ scdl pin open vreg_uv short circuit detection **) ena=low *) vs_uvlo **) ena=low *) vs_uvlo **) ena=low *) vs_uvlo **) ena=low *) vs_uvlo *) vs_uvlo
h-bridge and dual ha lf bridge driver ic TLE7181EM data sheet 18 rev 1.1, 2010-09-30 5.2.2 short circuit protection the TLE7181EM provides a short circuit protection for the external mosfets by monitoring the drain-source voltage of the external mosfets. this monitoring of the short circuit detection for a certain external mosfet is active as soon as the corresponding driver output stage is set to ?on? and the dead time and the blanking time are expired. the blanking time starts when the dead time has expire d and assures that the switch on process of the mosfet is not taken into account. it is recommended to keep th e switching times of the mosfets below the blanking time. the short circuit detection level is adjustable in an anal og way by the voltage setting at the scdl pin. there is a 1:1 translation between the voltage applied to the scdl pin and the drain-source voltage limit. e.g. to trigger the scd circuit at 1 v drain-source voltage, the scdl pin mu st be set to 1 v. the drain-source voltage limit can be chosen between 0.2 ... 2 v. if after the expiration of the blanking time the drain source volt age of the observed mosfet is still higher then the scdl level, the scd filter time t scp starts to run. a capacitor is charg ed with a current. if the capacitor voltage reaches a specific level (filter time t scp ), the error signal is set and the ic goes into scdl error mode. if the scd condition is removed before the sc is detected, the capa citor is discharged with the same current. the discharging of the capacitor happens as well when the mosfet is swit ched off. it has to be considered that the high side and the low side output of one phase are working with the same capacitor. 5.2.3 scdl pin open detection an integrated structure at the scdl pin assures that in case of an open pin the scdl voltage is pulled to a medium voltage level. the external mosfets are actively switched off and an err flag is set. this error is self-clearing. 5.2.4 vs and vdh over voltage warning the TLE7181EM has an integrated over voltage warning to mi nimize risk of destruction of the ic at high supply voltages caused by violation of the maximum ratings. for the over voltage warning the voltage is observed at the pin vs and vdh. if the voltage level has r eached, the fixed over voltage threshold v ovw for the filter time t ov, a warning at err pin is set and TLE7181EM will go in norm al operation with warning. the over voltage warning is self clea ring. if the voltage at pin vs and vdh returns into the specified voltage range, the error register will be cl eared and tle7181e m returns to norma l operation mode. it is the decision of the user, if and how to react on the over voltage warning. 5.2.5 vs under voltage shutdown the TLE7181EM has an integrated vs under voltage shutdown , to assure that the behavior of the complete ic is predictable in all supply voltage ranges. as soon as the under voltage threshold v uvvr is reached for a specified filter time the TLE7181EM is in vs_uvlo error mode. the error si gnal will be set and out put stages, voltage regulator and charge pump will be switched off so the ic will go into slee p mode. an enable is necessary to restart the TLE7181EM. 5.2.6 vreg under voltage warning the TLE7181EM has an integrated under voltage warnin g detection at vreg. if the supply voltage at vreg reaches the vreg under voltage threshold v uvvr , a warning at err pin is se t and the TLE7181EM will go into vreg error mode. in case of vreg error mode all output stages will active ly switched off to prevent low gate source voltages at the power mosfets causing high rds on. if supply voltage at the vreg pin recovers; the error flag will be cleared and the tle7181e m will return in norm al operation mode.
data sheet 19 rev 1.1, 2010-09-30 h-bridge and dual ha lf bridge driver ic TLE7181EM 5.2.7 over temperature warning the TLE7181EM provides an integrated digital over temper ature warning to minimize risk of destruction of the ic at high temperature. the temperature will be detected by a embedded sensor. during over temperature warning the err signal is set and the TLE7181EM is in normal operation mode with warning. the over temperature warning is self clearing. so if temperature is below t j(pw) - dt j(ow) , the warning will be cleared and TLE7181EM returns to normal operation mode. it is the decision of the user to react on the over temperature warning. 5.2.8 over current warning the TLE7181EM offers an inte grated over current detect ion. the output signal of the current sense opamp will be monitored. if the output signal reaches the specified voltage threshold v octh for a certain time, over current will be detected. after the comp arator the filter time t oc is implemented to avoid false triggering caused by overswing of the current sense signal. the err pin will be set to low and the tle7181e m will go into normal operation mode with warning. the error signal disappears as soon as the curr ent decreases below the over current threshold v octh . the error signal disappears as well when the current commutates fr om the low side mosfet to the associated high side mosfet and is no longer flowing over the shunt resistor. it is the decision of the user to react on the over current signal by modifying input patterns. 5.2.9 passive gxx clamping if vs under voltage shutdown is dete cted or the device is in sleep mode, a passive clamping is active as long as the voltage at vs or vdh is higher th an 3v. even below 3v it is assured that the mosfet driver stage will not switch on the mosfet actively. the passive clamping means that the bhx and the vreg pin are pulled to gnd with specified pull down resistors. together with the intrinsic diode of the push stage of the output stages which connec t the gate output to bhx respectively vreg, this assures th at the gate of the external mosfets are not floating undefined. 5.2.10 e rr pin the TLE7181EM has a status pin to provide diagnostic feedb ack to the c. the logical output of this pin is a push pull output stage with an integrated pull-down resistor to gnd (see figure 5 ). reset of error registers and disable the TLE7181EM can be reset by the enable pin ena. if the ena pin is pulled to low for a specified minimum time, the error register s are cleared. err out put is still set to low. af ter the next rising edge at ena pin err pin will be set to high and no error condition is applied.
h-bridge and dual ha lf bridge driver ic TLE7181EM data sheet 20 rev 1.1, 2010-09-30 figure 5 structure of err output table 4 overview of error condition table 5 prioritization of errors error logic c interface_ c gnd internal internal 5v err gnd tle718xem err driver conditions driver action restart high no errors fully functional ? low over temperature warning only self clearing low over voltage vs/vdh warning only self clearing low over current opamp warning only self clearing low under voltage error vreg all mosfets actively switched off self clearing low under voltage shutdown based on vs mosfet, charge pump, vreg switched off self clearing restart when enable high 1) low scdl open pin all mosfets actively switched off self clearing low short circuit detection all mosfets actively switched off reset at ena needed low go to sleep mode all mosfets actively switched off immediate restart when ena goes high low wake up mode start up ? 1) when sc detected, reset with ena necessary priority errors and warnings 0 under voltage lockout at vs (vs_uvlo) 1 short circuit detection error (scd) scdl pin open warning (scdlpod) 2 under voltage detection vreg (uv_vreg) over voltage detection warning (ovd) over temperature warning (otd) over current warning (ocd)
data sheet 21 rev 1.1, 2010-09-30 h-bridge and dual ha lf bridge driver ic TLE7181EM 5.2.11 electrical characteristics electrical characterist ics - protection and diagnostic functions v s = 7.0 to 34v, t j = -40 to +150 c , all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. short circuit protection 5.2.1 short circuit protection detection level input range v scdl 0.2 ? 2.0 v programmed by scdl pin 5.2.2 short circuit protection detection accuracy a scp1 -50 ? +50 % 0.2v v scdl 0.3v 5.2.3 short circuit protection detection accuracy a scp2 -30 ? +30 % 0.3v v scdl 1.2v 5.2.4 short circuit protection detection accuracy a scp3 -10 ? +10 % 1.2v v scdl 2.0v 5.2.5 filter time of short circuit protection t scp(off) 2.5 3.5 4.5 s ? 5.2.6 filter time and blanking time of short circuit protection t scpbt 468s? 5.2.7 internal pull-up resistor scdl to 3v r scdl 180 300 475 k ? 5.2.8 scdl open pin detection level v scpop 2.1 ? 3.2 v ? 5.2.9 filter time of scdl open pin detection t scpop 1.5 2.5 3.5 s ? 5.2.10 scdl open pin detection level hysteresis 1) v scoph ?0.3?v? over- and under voltage monitoring 5.2.11 over voltage warning at vs and/or vdh v ovw 34.5 36.5 38.5 v v vs and/or v vdh increasing 5.2.12 over voltage warning hysteresis for vs and/or vdh v ovwhys 2.1 3.1 4.1 v ? 5.2.13 over voltage warning filter time for vs and/or vdh t ov 13 19 25 s ? 5.2.14 under voltage shutdown at vs v uvvr 4.5 5.0 5.5 v v vs decreasing 5.2.15 under voltage shutdown filter time for vs 1) t uvlo ?20?s? 5.2.16 under voltage warning at vreg v uvvr 5.5 6.0 6.5 v v vs decreasing 5.2.17 under voltage diagnosis filter time for vreg t uvvr 10 ? 30 s ? 5.2.18 under voltage hysteresis at vreg v uwrhys ?0.5?v? temperature monitoring 5.2.19 over temperature warning t j(pw) 160 170 180 c ? 5.2.20 hysteresis fo r over temperature warning dt j(ow) 10 ? 20 c ? over current detection 5.2.21 over current detection level v octh 4.5 ? 4.99 v ?
h-bridge and dual ha lf bridge driver ic TLE7181EM data sheet 22 rev 1.1, 2010-09-30 5.2.22 filter time for over current detection t oc 2.3 ? 4.3 s ? err pin 2) 5.2.23 err output voltage v err 4.6??v v vs =7v; 5.2.24 rise time err (20 - 80% of internal 5v) t f(err) ??3s c load =1nf; 5.2.25 internal pull-down resistor err to gnd r f(err) 60 100 170 k ? 1) not subject to production test, specified by design. 2) err pin and reset & enable functional between v vs =6 ... 7v, but characteristics might be out of specified range electrical characterist ics - protection and diagnostic functions (cont?d) v s = 7.0 to 34v, t j = -40 to +150 c , all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max.
data sheet 23 rev 1.1, 2010-09-30 h-bridge and dual ha lf bridge driver ic TLE7181EM 5.3 shunt signal conditioning the TLE7181EM incorporates a fast and precise operational amplifier for conditioning and amplification of the current sense shunt signal. the gain of the opamp is adju stable by external resistors within a range higher than 5. the usage of higher gains in the application might be limited by required settling time and band width. it is recommended to apply a small offset to the opamp, to avoid operation in the lower rail at low currents. the output of the opamp iso is not short-circuit proof. figure 6 shunt signal conditioning block diagram and over current limitation over current warning see chapter 5.2.8 . 5.3.1 electrical characteristics electrical characteristics - current sense signal conditioning v s = 7.0 to 36v, t j = -40 to +150 c, gain = 5 to 75, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. 5.3.1 series resistors r s 100 500 1000 ? 5.3.2 feedback resistor limited by the output voltage dynamic range r fb 2000 7500 ? ? 5.3.3 resistor ratio (gain ratio) r fb/rs 5???? 5.3.4 steady state differential input voltage range across vin v in(ss) -400 ? 400 mv ? 5.3.5 input differential voltage (isp - isn) v idr -800 ? 800 mv ? 5.3.6 input voltage (both inputs - gnd) (isp - gnd) or (isn -gnd) v ll -800 ? 2000 mv ? 5.3.7 input offset volt age of the i-dc link opamp, including temperature drift v io ? ? +/-2 mv r s =500 ; v cm =0v; v iso =1.65v; 5.3.8 input bias current (isn,isp to gnd) i ib -300 ? ? a v cm =0v; v iso =open 5.3.9 low level output voltage of iso v ol -0.1 ? 0.2 v i oh =3ma external r s1 r s2 tle718xem - + - + v octh err r ref1 r fb r shunt v dd isn isp iso r ref2 r fb =(r ref1 ||r ref2 )
h-bridge and dual ha lf bridge driver ic TLE7181EM data sheet 24 rev 1.1, 2010-09-30 5.3.10 high level output voltage of iso v oh 4.75 ? 5.2 v i oh =-3ma 5.3.11 output short circuit current i scop 5??ma? 5.3.12 differential input resistance 1) r i 100??k ? 5.3.13 common mode input capacitance 1) c cm ? ? 10 pf 10khz 5.3.14 common mode rejection ratio at dc cmrr = 20*log((vout_diff/vin_diff) * (vin_cm/vout_cm)) c mrr 80 100 ? db ? 5.3.15 common mode suppression 2) with cms = 20*log(vout_cm/vin_cm) freq =100khz freq = 1mhz freq = 10mhz c ms ? 62 43 23 ?db v in =360mv* sin(2* *freq*t); r s =500 ; r fb =7500 5.3.16 slew rate d v/dt ?10?v/sgain 5; r l =1.0k ; c l =500pf 5.3.17 large signal open loop voltage gain (dc) a ol 80 100 ? db ? 5.3.18 unity gain bandwidth 1) g bw 10 20 ? mhz r l =1k ; c l =100pf 5.3.19 phase margin 1) f m ?50?gain 5; r l =1k ; c l =100pf 5.3.20 gain margin 1) a m ?12?db r l =1k ; c l =100pf 5.3.21 bandwidth b wg 0.7 1.3 ? mhz gain=15; r l =1k ; c l =500pf; r s =500 5.3.22 output settle time to 98% t set1 ? 1 1.8 s gain=15; r l =1k ; c l =500pf; 0.3< v iso < 4.8v; r s =500 5.3.23 output settle time to 98% 1) t set2 ? 4.6 ? s gain=75; r l =1k ; c l =500pf; 0.3< v iso < 4.8v; r s =500 1) not subjected to production test; specified by design 2) without considering any offsets such as input offset voltage, internal mismatch and assuming no tolerance error in external resistors. electrical characteristics - current sense signal conditioning (cont?d) v s = 7.0 to 36v, t j = -40 to +150 c, gain = 5 to 75, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max.
data sheet 25 rev 1.1, 2010-09-30 h-bridge and dual ha lf bridge driver ic TLE7181EM application information 6 application information note: the following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. this is the description how the ic is used in its environment? figure 7 application diagram 1: dc-brush motor controlled by TLE7181EM note: this are very simplified examples of an applicatio n circuit. the function must be verified in the real application. sh1 v bat c e.g.: xc878 gh1 gl1 vs pwm dir c vs1 2,2f r vs gnd isp gnd vreg tle 7181em pgnd ____ err iso shunt r s2 r s1 r fb ena isn bh1 c bs1 330nf r gh1 sh2 gh2 bh2 r gh2 c bs2 330nf r gl1 gl2 r gl2 l 2,2h gnd r iso sl r ref2 gnd gnd vdh c reg1 2,2f scdl r ref1 t ls 2 t ls 1 t hs2 t hs1 r sc1 r sc2 v dd v ref c snh1 r snh1 c snl1 r snl1 c snl2 r snl2 c snh2 r snh2 c b2 c c2 + c b1 c c1 + pgnd pgnd pgnd pgnd rpp gnd m dt r dt gnd c iso 100pf c is 50pf c vs2 10nf c reg2 10nf r g r fb =(r ref1 ||r ref2 ) drvdis r rps 4.7k
h-bridge and dual ha lf bridge driver ic TLE7181EM application information data sheet 26 rev 1.1, 2010-09-30 6.1 layout guide lines please refer also to the simplified application example. ? two separated bulk capacitors c b should be used - one per half bridge ? two separated ceramic capacitors c c should be used - one per half bridge ? each of the two bulk capacitors c b and each of the two ceramic capacitors c c should be assigned to one of the half bridges and should be placed very close to it ? the components within one half bridge should be placed close to each other: high side mosfet, low side mosfet, bulk capacitor c b and ceramic capacitor c c (c b and c c are in parallel) and the shunt resistor form a loop that should be as small and tight as possible. the traces should be short and wide ? the connection between the source of the high side mosfet and the drain of the low side mosfet should be as low inductive and as low resistive as possible. ? vdh is the sense pin used for short circuit detection; vdh should be routed (via rvdh) to the common point of the drains of the high side mosfets to sense the voltage present on drain high side ? sl is the sense pin used for short circuit detection; sl should be routed o the common point of the source of the low side mosfets to sense the voltage present on source low side ? additional r-c snubber circuits (r and c in series) can be placed to at tenuate/suppress oscillations during switching of the mosfets, there may be one or two snub ber circuits per half bri dge, r (several ohm) and c (several nf) must be low inductive in terms of routing and packaging (ceramic capacitors) ? if available the exposed pad on the backside of the package should be connected to gnd 6.2 further application information ? for further information you may contact http://www.infineon.com/
data sheet 27 rev 1.1, 2010-09-30 h-bridge and dual ha lf bridge driver ic TLE7181EM package outlines 7 package outlines figure 8 pg-ssop-24-4 green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). pg-ssop-24-4-po v01 1) does not include plastic or metal protrusion of 0.15 max. per side 112 24 13 2) does not include dambar protrusion of 0.13 max. 8.65 ?.1 c 0.1 a-b 2x 0.65 0.25 2) m c 0.2 d 24x ?.05 a-b b a index marking c (1.47) 1.7 max. 0.08 c seating plane ?.1 3.9 1) 0.35 x 45? ?.25 0.64 ?.2 d 6 m 0.2 d +0 -0.1 0.1 stand off +0.06 0.19 8? max. cd 2x 0.1 bottom view 24 1 6.4 ?.25 2.65 13 12 ?.25 for further information on alternativ e packages, please vi sit our website: http://www.infineon.com/packages . dimensions in mm
h-bridge and dual ha lf bridge driver ic TLE7181EM revision history data sheet 28 rev 1.1, 2010-09-30 8 revision history revision date changes 1.1 2010-09-30 datasheet max rating of current at rpp pin increased 1.0 2010-09-29 datasheet thermal resistance of package adjusted output rise time adjusted pull up and pull down resistor values adapted dead time values centered go to sleep time modified filter time of short circuit detection adjusted scdl pin open detection description improved overview of error condition table improved filter time and blanking time of short circuit detection adjusted scdl open pin detection level added filter time of scdl open pin detection adjusted over voltage warning at vs and/or vdh centered over voltage warning hysteresis for vs and/or vdh centered over voltage warning filter ti me for vs and/or vdh centered err output voltage added opamp bandwidth adjusted 0.8 2010-08-31 preliminary datasheet 0.7 2009-11-19 target data sheet 0.6 2008-30-10 target data sheet
edition 2010-09-30 published by infineon technologies ag 81726 munich, germany ? 2010 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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